subsurface/subsurfacesysinfo.h

/****************************************************************************
**
** Copyright (C) 2013 Digia Plc and/or its subsidiary(-ies).
** Copyright (C) 2014 Intel Corporation
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** Foundation and appearing in the file LICENSE.GPL included in the
** packaging of this file.  Please review the following information to
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#ifndef SUBSURFACESYSINFO_H
#define SUBSURFACESYSINFO_H

#include <QSysInfo>

#if QT_VERSION < 0x050000
#ifdef Q_OS_MACX
#  define Q_OS_OSX
#endif
#if defined(__arm__) || defined(__TARGET_ARCH_ARM) || defined(_M_ARM) || defined(__arm64__)
#	define Q_PROCESSOR_ARM
#	if defined(__arm64__)
#		define Q_PROCESSOR_ARM_64
#	else
#		define Q_PROCESSOR_ARM_32
#	endif
#	if defined(__ARM64_ARCH_8__)
#		define Q_PROCESSOR_ARM_V8
#		define Q_PROCESSOR_ARM_V7
#		define Q_PROCESSOR_ARM_V6
#		define Q_PROCESSOR_ARM_V5
#	elif defined(__ARM_ARCH_7__) \
	|| defined(__ARM_ARCH_7A__) \
	|| defined(__ARM_ARCH_7R__) \
	|| defined(__ARM_ARCH_7M__) \
	|| defined(__ARM_ARCH_7S__) \
	|| defined(_ARM_ARCH_7) \
	|| (defined(__TARGET_ARCH_ARM) && __TARGET_ARCH_ARM-0 >= 7) \
	|| (defined(_M_ARM) && _M_ARM-0 >= 7)
#		define Q_PROCESSOR_ARM_V7
#		define Q_PROCESSOR_ARM_V6
#		define Q_PROCESSOR_ARM_V5
#	elif defined(__ARM_ARCH_6__) \
	|| defined(__ARM_ARCH_6J__) \
	|| defined(__ARM_ARCH_6T2__) \
	|| defined(__ARM_ARCH_6Z__) \
	|| defined(__ARM_ARCH_6K__) \
	|| defined(__ARM_ARCH_6ZK__) \
	|| defined(__ARM_ARCH_6M__) \
	|| (defined(__TARGET_ARCH_ARM) && __TARGET_ARCH_ARM-0 >= 6) \
	|| (defined(_M_ARM) && _M_ARM-0 >= 6)
#		define Q_PROCESSOR_ARM_V6
#		define Q_PROCESSOR_ARM_V5
#	elif defined(__ARM_ARCH_5TEJ__) \
	|| defined(__ARM_ARCH_5TE__) \
	|| (defined(__TARGET_ARCH_ARM) && __TARGET_ARCH_ARM-0 >= 5) \
	|| (defined(_M_ARM) && _M_ARM-0 >= 5)
#		define Q_PROCESSOR_ARM_V5
#	endif
#	if defined(__ARMEL__)
#		define Q_BYTE_ORDER Q_LITTLE_ENDIAN
#	elif defined(__ARMEB__)
#		define Q_BYTE_ORDER Q_BIG_ENDIAN
#	else
// Q_BYTE_ORDER not defined, use endianness auto-detection
#endif


#elif defined(__i386) || defined(__i386__) || defined(_M_IX86)
#	define Q_PROCESSOR_X86_32
#	define Q_BYTE_ORDER Q_LITTLE_ENDIAN

#	if defined(_M_IX86)
#		define Q_PROCESSOR_X86     (_M_IX86/100)
#	elif defined(__i686__) || defined(__athlon__) || defined(__SSE__)
#		define Q_PROCESSOR_X86     6
#	elif defined(__i586__) || defined(__k6__)
#		define Q_PROCESSOR_X86     5
#	elif defined(__i486__)
#		define Q_PROCESSOR_X86     4
#	else
#		define Q_PROCESSOR_X86     3
#endif

#elif defined(__x86_64) || defined(__x86_64__) || defined(__amd64) || defined(_M_X64)
#	define Q_PROCESSOR_X86       6
#	define Q_PROCESSOR_X86_64
#	define Q_BYTE_ORDER Q_LITTLE_ENDIAN
#	define Q_PROCESSOR_WORDSIZE   8

#elif defined(__ia64) || defined(__ia64__) || defined(_M_IA64)
#	define Q_PROCESSOR_IA64
#	define Q_PROCESSOR_WORDSIZE   8

#elif defined(__mips) || defined(__mips__) || defined(_M_MRX000)
#	define Q_PROCESSOR_MIPS
#	if defined(_MIPS_ARCH_MIPS1) || (defined(__mips) && __mips - 0 >= 1)
#		define Q_PROCESSOR_MIPS_I
#	endif
#	if defined(_MIPS_ARCH_MIPS2) || (defined(__mips) && __mips - 0 >= 2)
#		define Q_PROCESSOR_MIPS_II
#	endif
#	if defined(_MIPS_ARCH_MIPS32) || defined(__mips32)
#		define Q_PROCESSOR_MIPS_32
#	endif
#	if defined(_MIPS_ARCH_MIPS3) || (defined(__mips) && __mips - 0 >= 3)
#		define Q_PROCESSOR_MIPS_III
#	endif
#	if defined(_MIPS_ARCH_MIPS4) || (defined(__mips) && __mips - 0 >= 4)
#		define Q_PROCESSOR_MIPS_IV
#	endif
#	if defined(_MIPS_ARCH_MIPS5) || (defined(__mips) && __mips - 0 >= 5)
#		define Q_PROCESSOR_MIPS_V
#	endif
#	if defined(_MIPS_ARCH_MIPS64) || defined(__mips64)
#		define Q_PROCESSOR_MIPS_64
#	endif
#	if defined(__MIPSEL__)
#		define Q_BYTE_ORDER Q_LITTLE_ENDIAN
#	elif defined(__MIPSEB__)
#		define Q_BYTE_ORDER Q_BIG_ENDIAN
#	else
// Q_BYTE_ORDER not defined, use endianness auto-detection
#endif


#elif defined(__ppc__) || defined(__ppc) || defined(__powerpc__) \
	|| defined(_ARCH_COM) || defined(_ARCH_PWR) || defined(_ARCH_PPC)  \
	|| defined(_M_MPPC) || defined(_M_PPC)
#	define Q_PROCESSOR_POWER
#	if defined(__ppc64__) || defined(__powerpc64__) || defined(__64BIT__)
#		define Q_PROCESSOR_POWER_64
#	else
#		define Q_PROCESSOR_POWER_32
#	endif

#elif defined(__s390__)
#	define Q_PROCESSOR_S390
#	if defined(__s390x__)
#		define Q_PROCESSOR_S390_X
#	endif
#	define Q_BYTE_ORDER Q_BIG_ENDIAN


#endif

// Some processors support either endian format, try to detect which we are using.
#if !defined(Q_BYTE_ORDER)
#	if defined(__BYTE_ORDER__) && (__BYTE_ORDER__ == Q_BIG_ENDIAN || __BYTE_ORDER__ == Q_LITTLE_ENDIAN)
// Reuse __BYTE_ORDER__ as-is, since our Q_*_ENDIAN #defines match the preprocessor defaults
#		define Q_BYTE_ORDER __BYTE_ORDER__
#	elif defined(__BIG_ENDIAN__) || defined(_big_endian__) || defined(_BIG_ENDIAN)
#		define Q_BYTE_ORDER Q_BIG_ENDIAN
#	elif defined(__LITTLE_ENDIAN__) || defined(_little_endian__) || defined(_LITTLE_ENDIAN) \
	|| defined(_WIN32_WCE) || defined(WINAPI_FAMILY) // Windows CE is always little-endian according to MSDN.
#		define Q_BYTE_ORDER Q_LITTLE_ENDIAN
#	else
#		error "Unable to determine byte order!"
#	endif
#endif

#ifndef Q_PROCESSOR_WORDSIZE
#	ifdef __SIZEOF_POINTER__
/* GCC & friends define this */
#		define Q_PROCESSOR_WORDSIZE        __SIZEOF_POINTER__
#	elif defined(_LP64) || defined(__LP64__) || defined(WIN64) || defined(_WIN64)
#		define Q_PROCESSOR_WORDSIZE        8
#	else
#		define Q_PROCESSOR_WORDSIZE        QT_POINTER_SIZE
#	endif
#endif
#endif // Qt < 5.0.0

class SubsurfaceSysInfo : public QSysInfo {
public:
#if QT_VERSION < 0x050400
	static QString buildCpuArchitecture();
	static QString currentCpuArchitecture();
	static QString buildAbi();

	static QString kernelType();
	static QString kernelVersion();
	static QString productType();
	static QString productVersion();
	static QString prettyProductName();
#endif
	static QString prettyOsName();
};


#endif // SUBSURFACESYSINFO_H